/**
 * @file
 * @brief GD32VFmwLib：中断向量表
 * @author
 * + 隐星魂 (Roy Sun) <xwos@xwos.tech>
 * @copyright
 * + Copyright © 2015 xwos.tech, All Rights Reserved.
 * > Licensed under the Apache License, Version 2.0 (the "License");
 * > you may not use this file except in compliance with the License.
 * > You may obtain a copy of the License at
 * >
 * >         http://www.apache.org/licenses/LICENSE-2.0
 * >
 * > Unless required by applicable law or agreed to in writing, software
 * > distributed under the License is distributed on an "AS IS" BASIS,
 * > WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * > See the License for the specific language governing permissions and
 * > limitations under the License.
 */

#include "GD32VFmwLib/std.h"
#include <xwos/ospl/irq.h>
#include <xwos/ospl/skd.h>
#include <xwos/ospl/syshwt.h>
#include "GD32VFmwLib/ivt/isr.h"
#include "gd32vf103.h"

__eclic_ivt xwisr_f eclic_ivt[ECLIC_NUM_INTERRUPTS] = {
        [SOC_IRQn_Reserved0] = Reserved0_IRQHandler,
        [SOC_IRQn_Reserved1] = Reserved1_IRQHandler,
        [SOC_IRQn_Reserved2] = Reserved2_IRQHandler,
        [SOC_IRQn_SysTimerSW] = xwospl_skd_isr_swcx,
        [SOC_IRQn_Reserved3] = Reserved3_IRQHandler,
        [SOC_IRQn_Reserved4] = Reserved4_IRQHandler,
        [SOC_IRQn_Reserved5] = Reserved5_IRQHandler,
        [SOC_IRQn_SysTimer] = xwospl_syshwt_isr,
        [SOC_IRQn_Reserved6] = Reserved6_IRQHandler,
        [SOC_IRQn_Reserved7] = Reserved7_IRQHandler,
        [SOC_IRQn_Reserved8] = Reserved8_IRQHandler,
        [SOC_IRQn_Reserved9] = Reserved9_IRQHandler,
        [SOC_IRQn_Reserved10] = Reserved10_IRQHandler,
        [SOC_IRQn_Reserved11] = Reserved11_IRQHandler,
        [SOC_IRQn_Reserved12] = Reserved12_IRQHandler,
        [SOC_IRQn_Reserved13] = Reserved13_IRQHandler,
        [SOC_IRQn_Reserved14] = Reserved14_IRQHandler,
        [SOC_IRQn_BusError] = BusError_IRQHandler,
        [SOC_IRQn_PerfMon] = PerfMon_IRQHandler,

        [WWDGT_IRQn] = WWDGT_IRQHandler,
        [LVD_IRQn] = LVD_IRQHandler,
        [TAMPER_IRQn] = TAMPER_IRQHandler,
        [RTC_IRQn] = RTC_IRQHandler,
        [FMC_IRQn] = FMC_IRQHandler,
        [RCU_CTC_IRQn] = RCU_CTC_IRQHandler,
        [EXTI0_IRQn] = EXTI0_IRQHandler,
        [EXTI1_IRQn] = EXTI1_IRQHandler,
        [EXTI2_IRQn] = EXTI2_IRQHandler,
        [EXTI3_IRQn] = EXTI3_IRQHandler,
        [EXTI4_IRQn] = EXTI4_IRQHandler,
        [DMA0_Channel0_IRQn] = DMA0_Channel0_IRQHandler,
        [DMA0_Channel1_IRQn] = DMA0_Channel1_IRQHandler,
        [DMA0_Channel2_IRQn] = DMA0_Channel2_IRQHandler,
        [DMA0_Channel3_IRQn] = DMA0_Channel3_IRQHandler,
        [DMA0_Channel4_IRQn] = DMA0_Channel4_IRQHandler,
        [DMA0_Channel5_IRQn] = DMA0_Channel5_IRQHandler,
        [DMA0_Channel6_IRQn] = DMA0_Channel6_IRQHandler,
        [ADC0_1_IRQn] = ADC0_1_IRQHandler,
        [CAN0_TX_IRQn] = CAN0_TX_IRQHandler,
        [CAN0_RX0_IRQn] = CAN0_RX0_IRQHandler,
        [CAN0_RX1_IRQn] = CAN0_RX1_IRQHandler,
        [CAN0_EWMC_IRQn] = CAN0_EWMC_IRQHandler,
        [EXTI5_9_IRQn] = EXTI5_9_IRQHandler,
        [TIMER0_BRK_IRQn] = TIMER0_BRK_IRQHandler,
        [TIMER0_UP_IRQn] = TIMER0_UP_IRQHandler,
        [TIMER0_TRG_CMT_IRQn] = TIMER0_TRG_CMT_IRQHandler,
        [TIMER0_Channel_IRQn] = TIMER0_Channel_IRQHandler,
        [TIMER1_IRQn] = TIMER1_IRQHandler,
        [TIMER2_IRQn] = TIMER2_IRQHandler,
        [TIMER3_IRQn] = TIMER3_IRQHandler,
        [I2C0_EV_IRQn] = I2C0_EV_IRQHandler,
        [I2C0_ER_IRQn] = I2C0_ER_IRQHandler,
        [I2C1_EV_IRQn] = I2C1_EV_IRQHandler,
        [I2C1_ER_IRQn] = I2C1_ER_IRQHandler,
        [SPI0_IRQn] = SPI0_IRQHandler,
        [SPI1_IRQn] = SPI1_IRQHandler,
        [USART0_IRQn] = USART0_IRQHandler,
        [USART1_IRQn] = USART1_IRQHandler,
        [USART2_IRQn] = USART2_IRQHandler,
        [EXTI10_15_IRQn] = EXTI10_15_IRQHandler,
        [RTC_ALARM_IRQn] = RTC_ALARM_IRQHandler,
        [USBFS_WKUP_IRQn] = USBFS_WKUP_IRQHandler,

        [TIMER4_IRQn] = TIMER4_IRQHandler,
        [SPI2_IRQn] = SPI2_IRQHandler,
        [UART3_IRQn] = UART3_IRQHandler,
        [UART4_IRQn] = UART4_IRQHandler,
        [TIMER5_IRQn] = TIMER5_IRQHandler,
        [TIMER6_IRQn] = TIMER6_IRQHandler,
        [DMA1_Channel0_IRQn] = DMA1_Channel0_IRQHandler,
        [DMA1_Channel1_IRQn] = DMA1_Channel1_IRQHandler,
        [DMA1_Channel2_IRQn] = DMA1_Channel2_IRQHandler,
        [DMA1_Channel3_IRQn] = DMA1_Channel3_IRQHandler,
        [DMA1_Channel4_IRQn] = DMA1_Channel4_IRQHandler,

        [CAN1_TX_IRQn] = CAN1_TX_IRQHandler,
        [CAN1_RX0_IRQn] = CAN1_RX0_IRQHandler,
        [CAN1_RX1_IRQn] = CAN1_RX1_IRQHandler,
        [CAN1_EWMC_IRQn] = CAN1_EWMC_IRQHandler,
        [USBFS_IRQn] = USBFS_IRQHandler,

};

__soc_ivt const struct soc_ivt soc_ivt = {
        .exc = soc_evt,
        .irq = eclic_ivt,
};
